| A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memoryspace, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressingmode, source and destination pointers, and transfer count) is configured with DMA descriptors anywhere inmemory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achievehighly efficient operation by using the DMA controller for data transfers between SFR or XREG addresses andflash/SRAM.Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit periodvalue, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each ofthe counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. Itcan also be configured in IR Generation Mode, where it counts Timer 3 periods and the output is ANDed withthe output of Timer 3 to generate modulated consumer IR signals with minimal CPU interaction.Timer 2 (the MAC Timer) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slottedprotocol in software. The timer has a configurable timer period and a 24-bit overflow counter that can be used tokeep track of the number of periods that have transpired. A 40-bit capture register is also used to record theexact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmissionends, as well as two 16-bit output compare registers and two 24-bit overflow compare registers that can sendvarious command strobes (start RX, start TX, etc.) at specific times to the radio modules.Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmableprescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each ofthe counter channels can be used as a PWM outpu |
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